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  • 期刊名称:

    Solid-State Electronics

  • 中文名称: 固态电子
  • 刊频: 1.494
  • ISSN: 0038-1101
  • 出版社: -
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  • 机译 GaN TFET,FinFET和GNRFET技术中的8T静态RAM单元的低功耗-高速性能-评论
    摘要: Recent ULSI technology development emphasizes both silicon and graphene-based devices and system performance in terms of their low power and high switching speed. With Moore's law scaling having reached the limits of physics due to ballistic effects, efforts are moving towards nano scale materials and devices such as TFETs and GNRFETs. Still, recent developments with 7 nm lithography-based silicon devices have cited exciting results. The successful development of FinFET devices in integrated systems has been a breakthrough for the semiconductor industry. Research efforts were emphasized for new nanoscale materials such as Graphene, GaN, and Carbon nanotubes, as alternative devices for ULSI integrated system design. This paper provides a cumulative review for these three nanoscale devices: FinFET, TFET, and GNRFET. The study focuses on an 8T SRAM cell as geared towards low power and high-speed features that are suitable for high speed computers, wireless communications, and medical devices. The study covers device theory, models, and simulation. The study has showed evidence that the power consumption for both TFET and GNRFET -based systems features superior low power performance of a ratio 1:0.24 as taken for the Static T Cell for 20 nm scale devices. The practical model of the FinFET is verified and used by industry, while the practical model of both TFET and GNRFET are still in the prototype stage.
  • 机译 单晶半导体层厚度受控分离的剥落技术解析模型
    摘要: Thickness-controlled separation of a thin layer of single-crystalline semiconductors from its bulk substrate has been developed for the co-integration of compound semiconductors with silicon-based integrated circuit chips and the fabrication of high-performance flexible devices. Recently, a controlled spalling technique that can mechanically separate single-crystalline semiconductor layers has been actively demonstrated because of the process simplicity and the less limitation on the use of materials. Here, we developed an analytic model that can precisely estimate the spalling depth. In this model, the spalling depth was calculated from the thermodynamic equilibrium condition in which total strain energy accumulated in a separated layer is balanced with the crystal binding energy. We experimentally investigated the dependence of the spalling depth on the stressor layer thickness and stress, and we compared the empirical results with the proposed analytic model. We also verified that the crack initiation angle of the spalling process is determined by the binding energy contrast in the main crystal orientations in the semiconductor.
  • 机译 使用具有两个独立控制门的非对称浮栅MOSFET的输入调制自适应神经元电路
    摘要: In this paper, we present an input-modulating adaptive neuron circuit employing a floating-gate MOSFET (FG-MOSFET) with two asymmetrically shaped control gates. The proposed FG-MOSFET is utilized as key element for implementing neural adaptation in integrate-and-fire (I&F) neuron circuit. To confirm current modulating capability of proposed device, an adjustable-gain current mirror employing the device is simulated as well. Adaptive neuron circuit presented in this paper successfully exhibits spike-triggered adaptation with ratio between maximum and minimum firing rate ranging from 7.97 to 18.4. Compared to conventional researches, adaptive neuron circuit proposed in this paper allows more versatile operation and easier fabrication due to utilization of out FG-MOSFET.
  • 机译 通过掺入嵌入了银纳米颗粒的聚苯胺作为缓冲层来改进有机太阳能电池
    摘要: The role of silver nanoparticles (AgNP) in polyaniline (PANI) as a buffer layer for ITO/AgNP-PANI/PANI/Al solar cell was investigated. It is observed that AgNP-PANI buffer layer significantly improves the electrical parameters such as diode-ideality factor, series-resistance, energy-barrier height, and shunt-resistance as a growing function of AgNP concentration. On-the-other hand oppose to the dark current-voltage response, 0.5% concentration of AgNP in buffer layer shows the most optimum photovoltaic response and cause to increase the power conversion efficiency (PCE) nearly 5 times compared to same solar cell without buffer layer. Such improvements in electrical parameters can be interpreted as the reduction in interfacial trap states as well as enhancement in interfacial dipole-moment by AgNP embedded buffer layer for given photovoltaic device. While, the observed optimum photovoltaic behavior at 0.5% AgNP concentration is may be due to the trade-offs between gains and losses for optical absorption enhancement, self-absorption heating and interface recombination losses respectively. It is also observed that the AgNP embedded PANI buffer layer approach is an effective solution to lower the photovoltaic degradation and hence improves the stability of the photovoltaic devices.
  • 机译 磁性隧道结中随机电阻态的数字读出优化
    摘要: True random number generators (TRNGs) provide a wide area of applications and can be fabricated on the basis of magnetic tunnel junctions (MTJs). This work represents the modeling of TRNG readout optimization, where the induced digital random bit is detected within only a single computational period. The period contains two sub-cycles: write and joined read & reset cycles. The system has a valuable potential to become stochastically independent after calibrating at the desired working point against the factors, which cause to the signal deviations: temperature-induced, material degradation or other problems.
  • 机译 PZT薄膜压电微激励器通过直流偏置预极化的可调响应
    摘要: PZT piezoelectric thin film based technology is promising in the field of micro-actuators. This paper discusses the effects of pre-polarization on the key properties of PZT thin film, and explores the improvement rules of pre-polarization from the material to device level experiments. At the material level, the pre-polarization treatment increases the piezoelectric strain coefficient by 25%, and improves dielectric properties. Meanwhile, in ferroelectric properties the pre-polarization treatment increases the residual polarization by 50% and coercive field by 25%, respectively. At the device level, pre-polarization treatment greatly increases the output characteristics of the devices, such as maximum output displacement increasing by at least 45% and withstand voltage enhancing by 2 V, which is consistent with the material level enhancement. In addition, the optimal pre-polarization process conditions and the long-term stability of the performance improvement are investigated. The prepolarization treatment has proved to be meaningful for the improvement of the output capability of the piezoelectric thin film actuators.
  • 机译 基于HBT的Ⅲ-Ⅴ族化合物半导体的经验噪声模型
    摘要: This paper presents a novel approach for the modeling of noise behavior of III-V compound semiconductor based HBT's over a wide frequency range. The main advantage is that the proposed model is based on two individual un-correlated noise sources, and easy to be incorporated with commercial circuit simulation software. The model is verified by measurements of the four noise parameters of an InP HBT up to 20 GHz and a GaAs HBT up to 26 GHz. The good agreements have been obtained.
  • 机译 用于高线性度和低损耗RF电路应用的数字可调小面积复合变容二极管阵列,采用正负控制电压工作
    摘要: A small-area composite-varactor-based digitally tunable capacitor operated with positive and negative control voltages is proposed to remove several drawbacks resulting from the metal-insulator-metal (MIM) capacitor of the conventional switched capacitor array (SCA). It was constructed with several composite-varactor branches in parallel, each of which consists of p-type (P+/Pwell) and n-type (N+/Nwell) accumulation-mode varactors in a cascode configuration. The optimum ratio of the channel width between p-type and n-type accumulation-mode varactors was investigated through the simulation in order to maximize a quality factor (Q-factor) of the tunable capacitor at the maximum capacitance (C-MAX) state. The number of composite-varactor unit in each branch was designed to be binary-weighted, and the total capacitance can vary linearly by digitally turning on and off both varactors. It was firstly implemented in 65-nm bulk CMOS process, and showed comparable tuning range, Q-factor, and harmonic distortion performances while reducing the silicon area by half and eliminating the MIM capacitor in comparison with the conventional SCA. In the measurement, the proposed tunable capacitor showed a Q-factor of 60.3 at C-MAX state and a tuning range of 2.8 at 2 GHz frequency band. In addition, it was perfectly capable of handling a high power signal up to 0 dBm with excellent second and third-order harmonic distortion of greater than 70 dBc at the minimum capacitance (C-MIN) state and 77 dBc at C-MAX state.
  • 机译 电容电压技术表征低温多晶硅薄膜晶体管沿沟道的横向陷阱位置
    摘要: This study introduces a characterization technique for trap locations (X-t) with considerable trap density along the channel in field effect transistors (FETs). The technique is based on the experimental gate-to-source or gateto-drain capacitance-voltage (C-GS-V-GS or C-GD-V-GD) characteristics of FETs. As the gate bias (V-G) increases, the effective channel length (L-eff) extends by the increased conductivity of the channel from the source or the drain. Due to trapped charges at the trap sites with a high density of traps along the channel, abrupt change in the C-V characteristics is observed. For the transition gate bias (V-G,V-t) with abrupt change in the C-V characteristics, the dominant trap location (X-t) can be converted through the channel conduction factor (alpha(V-G) to be the effective channel length L-eff(V-G) = alpha(V-G).L-ch). We expect that the proposed C-V technique to be useful in non-destructive electrical characterization of lateral trap locations (interface states, bulk traps, and/or grain boundary traps caused by the bias stress and/or fabrication process) along the channel in FETs. We successfully applied the proposed technique to the p-channel poly-Si thin-film transistors (TFTs) for characterization of the grain boundary locations along the channel. As an example for the proposed technique, we applied the technique to a p-channel poly-Si TFT and obtained a dominant trap at X-GB1 = 3.13 [mu m] from the source and another at X-GB2 = 3.70 [mu m] from the drain.
  • 机译 CMOS FDSOI技术实现的单光子雪崩二极管的间接雪崩事件检测
    摘要: In this letter, a novel indirect avalanche event detection is proposed and demonstrated for Single Photon Avalanche Diodes (SPADs) implemented in CMOS 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. This approach is based on the capacitive coupling between the P-well, i.e. SPAD anode, and the transistor channel, separated by the ultra-thin buried oxide. The associated body-biasing effect is used to dynamically modulate the output of a simple voltage divider synchronously with the SPAD activity. A test-chip has been designed, fabricated and characterized to validate the proposed approach. This novel architecture opens the way for innovative SPAD processing circuitry implemented in 3D native CMOS FDSOI.
  • 机译 考虑负差分跨导(NDT)的隧道场效应晶体管(TFET)的设计指南
    摘要: A gate-normal tunnel field-effect transistor (TFET) showing negative differential transconductance (NDT) and its design guideline are proposed. The introduction of the source depletion to the gate-normal TFETs leads to negative differential transconductance. It is also confirmed that the NDT of the proposed gate-normal TFET is successfully enhanced by modulating gate-induced source depletion effects.
  • 机译 基于阻抗谱的热电模块等效因数模型(ZT)
    摘要: Impedance spectroscopy is able to simultaneously extract three key parameters, namely, the Seebeck coefficient, electrical conductivity, and thermal conductivity, leading to determination of the figure of merit (ZT). As the measurement method is simple, it can be used conveniently at room temperature. However, when measuring at high temperatures, there are restrictions on the IS method. Electrical parasitic parameters between the measuring equipment and the temperature chamber may reduce the reliability of the characterization. Since the electrical part connecting the temperature-variable chamber to the measuring equipment can have tens to hundreds of milliohms, it should be considered as lumped parameters in order to evaluate the intrinsic component of the thermoelectric module. In this study, the electrical and thermal characteristics of the Bi2Te3 thermoelectric module were evaluated in the range from room temperature to 150 degrees C using an impedance spectroscopy-based electrical equivalent model (ISEEM). The ISEEM includes an impedance component consisting of the thermoelectric module itself and the parasitic electrical impedance constituting the measuring apparatus, where the electrical impedance of the measuring equipment can be evaluated by the de-embedding method. As a result, it is possible to accurately extract the intrinsic characteristics of the Bi2Te3 thermoelectric module through ISEEM. The intrinsic parameters of a commercial thermoelectric module of 40 mm by 40 mm were obtained within an error rate of 5% regardless of the peripheral measuring device. Consequently, the module had a ZT maximum value of 0.73 at 22 degrees C and a performance of 0.49 at 150 degrees C. These results demonstrate that electrical and thermal characterization can be performed easily, and at the same time, the reliability of the characterization can be improved.
  • 机译 了解金属氧化物引起的有机晶体管接触电阻的降低
    摘要: It is well known that inserting metal oxides on top of electrodes in coplanar bottom-gate bottom-contact organic field-effect transistors (OFETs) improves the OFET performance in terms of increased current density, higher effective mobility and reduced contact resistance. This elucidates the transistor performance gain in case of oxidized metal electrodes using numerical device simulations and experimental data. The study strongly supports the hypothesis that the impact of oxidization can be explained for these experiments by an improvement of the semiconductor morphology in the vicinity of oxidized electrodes in conjunction with an improved mobility in these regions.
  • 机译 用于在动态工作条件下SiGe HBT中热载流子降解的物理和通用老化紧凑模型
    摘要: This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick's law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.
  • 机译 通过等离子体增强原子层沉积生长的BeO薄膜的介电性能得到改善
    摘要: Beryllium oxide (BeO) thin films were grown on a p-type Si substrate by plasma enhanced atomic layer deposition (PEALD) using diethylberyllium as a precursor and O-2 plasma. The PEALD BeO exhibited self-saturation and linear growth rates. The dielectric properties of PEALD were compared with those of thermal atomic layer deposition (ThALD). X-ray photoelectron spectroscopy was performed to determine the bandgap energy of PEALD BeO (8.0 eV) and ThALD BeO (7.9 eV). Capacitance-voltage curves revealed that PEALD BeO had low hysteresis and frequency dispersion compared to ThALD BeO. In addition, PEALD showed a dielectric constant of 7.15 (at 1 MHz) and low leakage current (7.25 x 10(-9) A/cm(2) at -1 MV/cm). These results indicate that the highly activated radicals from oxygen plasma prompt the chemical reaction at the substrate, thus reducing nucleation delay and interface trap density.
  • 机译 非晶Cd-In-O薄膜中电离势的调谐
    摘要: Ionization potential is an important parameter for the design of semiconductor devices. Since amorphous semiconductors do not have long-range ordering and lattice constants, it is not necessary to consider lattice defects at interfaces. If the ionization potential can be controlled with such an amorphous semiconductor, the flexibility of the semiconductor device designs will expanded. This enables the fabrication of semiconductor devices such as light-emitting diodes, laser diodes, and solar cells. In this study, we fabricated n-type amorphous Cd-In-O films (a-CIO) on silica glass substrates using radio frequency magnetron sputtering at room temperature. The band gaps of these films increased from 2.6 to 3.0 eV with a decrease in the Cd concentration (Cd/ (Cd+ In)). I-p (energy difference between the vacuum level (E-vac) and the valence band maximum) and electron affinity (the difference between the E-vac and the conduction band minimum) were measured using a combination of ultraviolet photoelectron spectroscopy and optical spectroscopy techniques. I(p)s were controlled by the Cd concentration in films without a shift in electron affinities. The results suggest that the a-CIO films are suitable for the design of semiconductor devices such as solar cells, where tuning the I-p is important.
  • 机译 凹陷深度对使用HfO_2栅绝缘体的Si衬底上AlGaN / GaN功率MIS-HEMT性能的影响以及不同凹陷深度的阈值电压模型
    摘要: Three types of E-mode AlGaN/GaN MIS-HEMTs with different barrier depths and conventional HEMT were fabricated on the Si substrates. HfO2 gate insulator with a thickness of 30 nm was grown by plasma enhanced atomic layer deposited (PEALD). Characteristics of the four devices with different recess depths are analyzed. The MIS-HEMT with barrier layer thickness of 3 nm features good comprehensive performance. The threshold voltage (V-th) is 1.8 V, the drain current density is 480 mA/mm and the figure of merit (FOM) is 363 MW/cm(2). When the barrier thickness is 0 nm, the V-th is up to 3.7 V. A calculation model of threshold voltage for recessed MIS-HEMTs is proposed. When the barrier layer thickness is 6 nm, the calculated value of V-th was 0.3 V which is in good match with the experimental value of 0.4 V. The proposed model provides guidelines for the AlGaN/GaN MIS-HEMTs designs.
  • 机译 先进FD-SOI MOSFET栅极泄漏电流及其晶圆级可变性的建模与分析
    摘要: The gate leakage current in advanced FD-SOI devices are investigated using systematic measurements on multiple geometry devices from 14 nm node. A simple model with an equivalent trapezoidal barrier based on WKB approximation is introduced and verified on the different measurements. The wafer level variability of the leakage current is explored using statistical modelling and the simple model for gate leakage current. The pure physical sources of variation are identified and the scaling trends of the standard deviations of the sources are analysed. The methodology and models have been validated also on 28 nm node devices.
  • 机译 铁电门控纳米机电二极管非易失性存储单元的理论研究
    摘要: Based on the polarization property and negative-capacitance (NC) effect of ferroelectric capacitors, nanoelectromechanical (NEM) diode nonvolatile memory cells (NC-NEM diode NVMs) are proposed for use in random-access memory arrays. It is observed that, by optimizing the structural parameters of the NEM memories, the NC-NEM diode NVMs can achieve more scaled program/erase voltages and better switching delays, when compared to the existing NEM diode memories. Moreover, the NC-NEM diode NVM has a one-directional current path, which is desirable in random-access memory arrays to block the sneak leakage.
  • 机译 使用热发光显微镜对基于CMOS的红外光源进行高温表征
    • 作者:;
    • 刊名:Solid-State Electronics
    • 2020年第Apr.期
    摘要: This paper presents the high temperature thermal characterization of a Micro-Electro-Mechanical Systems (MEMS) infra-red (IR) thermal source, using non-contact optical approaches, based on IR and thermo-incandescence microscopy. The IR thermal source was fabricated using a CMOS based processing technology and consists of a miniature micro-heater, fabricated using tungsten metallization. The performance and reliability of the IR source is highly dependent on its operating temperature. For short-wave (1.4 mu m-2.5 mu m) infra-red emission, the operating temperature is in excess of 800 degrees C. Work will be presented in this paper in which spot temperature measurements ( > 700 degrees C) were made on the IR source using thermal-incandescence microscopy. Thermal-optical calibration was achieved by utilizing the known melting point (MP) of different metal microparticles. Optical measurements were compared to those obtained using an electrical approach. The thermal measurements suggest good temperature uniformity across the micro-heater of the IR source.
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